In the fabrication of IC devices, a frequently seen mode of failure results form stress and strain in the bulk material used in forming the device. The stress and strain in the bulk material may be caused by the internal forces due to dislocations, excess vacancies and impurities in the material, growth around trapped foreign material, thermal gradients during processing, and changes in temperature after dissimilar materials are bonded together. For instance, vapor-deposited material of either an amorphous type, a polycrystalline type or a single-crystal type develops large internal stresses during the deposition process.
The stress and strain problem frequently occurs in the thin films formed of dissimilar materials on top of a silicon wafer. These dissimilar materials may be silicon, silicon oxide, metal conducting layers, passivation dielectric layers and polymeric based molding materials used in the encapsulation process. The structural built-up of wafers normally involves semiconductor-dielectricmetal sandwiching layers that are particularly susceptible to differential expansion-induced stress because of the large disparity between the thermal expansion coefficients of the various materials. In addition, the various films of different materials may have internal stresses built-in during the deposition process which may further increase the thermally-induced stress.
To determine the magnitude and the detrimental effect of the differential expansion-induced stress in an IC device, therefore, becomes an important task in the quality control or reliability determination of device fabricated. The type of reliability problems that are frequently seen in molded plastic packages of IC devices frequently involves cracking in the layers of thin films deposited on the silicon surface. A hot/cold thermal cycle test is one method used in reliability testing for determination of the differential expansion-induced stress, also known as thermo-mechanical stress resulting from disparity of expansion coefficience of the material layers which causes large relative displacements at the various material interfaces.
In an IC device that is formed with dies of substantially square dimensions, it has been noticed that the differential expansion-induced stress occurs most severely at the corner regions of the dies. The stress exists mostly in a form of shear stress between the material layers. The shear stress may severely affect the isolation between dielectric layer and metal layers and furthermore, the adhesion between a silicon oxide layer and a silicon surface thus presenting various reliability problems. Since most of the materials used in forming the metal layers, the dielectric layers and the isolation layers are fixed and cannot be changed, the selection of a plastic molding compound for encapsulating the IC package becomes an important factor. The selection of the molding compound must be carefully conducted such that the differential expansion-induced stress caused by a disparity of expansion coefficient between the molding compound and the various material layers must be minimized. It is therefore desirable to have an IC test die that can be formed with built-in stress test patterns for evaluating the undesirable effect of the different expansion coefficient between the materials.
It is therefore an object of the present invention to provide an IC die that is formed with built-in stress test pattern that does not have the drawbacks or shortcomings of the conventional test methods for molded-in stresses on IC packages.
It is another object of the present invention to provide an IC die that is formed with built-in stress test pattern that can be easily fabricated during the IC die fabrication process.
It is a further object of the present invention to provide an IC die that is formed with built-in stress test pattern without requiring additional fabrication steps than those normally required for forming the die.
It is another further object of the present invention to provide an IC die that is formed with built-in stress test pattern at corner regions of the die.
It is still another object of the present invention to provide an IC die that is formed with built-in stress test pattern that includes at least two stress patterns each formed at one of the four corner regions.
It is yet another object of the present invention to provide an IC die that is formed with at least two stress test patterns wherein each of the patterns is formed with a dielectric layer on the silicon substrate, a first metal layer, an electrically insulating material layer, and a second metal layer on top while the die is encapsulated in a molding compound.
It is still another further object of the present invention to provide a method for testing thermo-mechanical stresses in a plastic package of an IC die by first providing an IC die with built-in test patterns formed at least two of the comer regions, encapsulating the die in a molding compound, thermal cycling the package through a plurality of thermal cycles, and probing between the first and second plurality of metal traces in the test pattern to determine leakage currents and thermo-mechanical stresses.
It is yet another further object of the present invention to provide a method for testing thermo-mechanical stresses in a plastic package of an IC die by first forming built-in stress test patterns at a comer region which consists of a first metal layer formed in linear metal traces and a second metal layer formed in L-shaped metal bars on top of the first metal layer with an electrically insulating layer therein between.